*Requirements:

• Should have managed more than one program from Synthesis to GDSII activities.
• Should have handled team of 6-10 members under his guidance.
• Should have strong knowledge of Physical Design Methodologies (LowPower, Sub-16nm, Hierarchical)
• Should have worked on Fullchip and Block-Level PD Activities (Hierarchical Floorplanning, Place and Route, Timing Closure).
• Should have proficiency with either Synopsys (ICC2) or Cadence (Innovus) Tool Platform. Preferred Synopsys-ICC2, Fusion Compiler
• Should be good at Crosstalk, EM/IR, Timing Closure, Physical Verification Signoff Activities
• Should have knowledge of Programming Languages:  Shell, Make, TCL, Perl
• Should have strong communication and presentation skills (written and oral)