Purpose of the job 
Responsible for RTL engineer from concept study, architecture definition, design and verification, to silicon bring-up and characterization. 

Responsibilities 
- Study the requirements of the digital functions then describe the logic functionalities of the design in form block diagrams, data flow diagram, algorithm state machine, finite state machines, and detailed timing charts. 
- Implement RTL in Verilog/System Verilog, perform unit level testing, debug tests, SDC and UFP generation. 
- Perform RTL Lint check, RTL synthesis, Equivalence checking, CDC checking and support Static Timing Analysis. 
- Make sure designs are delivered on time and with the highest quality by using proper checks. 
- Resolve technical issues in developing digital blocks, gate level simulation, power and static timing analysis with team members. 
- Work with verification team for test plan/strategy to meet all functional requirements and performance 
- Work with timing and physical team for timing closure and meet power and area goals 
- Support project managers with effort estimations and resource planning 
- Support team leader in coaching, training and development team members.   

Requirements 
- Education Required: University and higher 
- Major: Electrical and Electronics, Computer science or related majors 
- Experience: Not required Experience (Accept Fresher) 
- Job related requirements:  

• Good experience in digital design flow including: RTL coding, RTL simulation, logic synthesis, timing constraints, timing closure, STA, gate level simulation and equivalence checking. 
• Very skilled in Hardware Description Languages: Verilog and System Verilog. 
• Familiar with JIRA project management system and git control system. 

- Other requirements 

• Good communication skills in English and have excellent interpersonal communication skills and ability to work in large international teams. 
• Logical thinking 
• Research and apply new technology 
• Analytic and troubleshoot problem 
• Careful 
• Ability to multi-task and can work under deadline pressure.