I. Purpose of the Job
- Responsible for all aspects of the SoC physical design flow including but not limited to: floor-planning, place and route, timing and power, physical verification, and full chip design database ready for manufacturing.

II. Main Functions
- Work with the FE team to understand chip architecture and dependencies between different domains then drive physical aspects early in design cycle.
- Responsible for full chip physical design both flat and hierarchical.
- Create full chip floor plan including pin placement, partitions and power grid.
- Develop and validate high performance low power clock network guidelines.
- Perform block level place, route and close the design to meet timing, area and power constraints.
- Generate and implement ECOs to fix timing, noise and EM IR violations.
- Run Physical design verification flow at chip/block level and come up with guidelines and checklist, execute and track progress.
- Work with expert team to identify potential solution, drive execution and improvement in PD work methodologies.
- Manage, assist, and resolve technical issues related to PD work with team members.
- Work with counterparts in other sites to jointly execute projects as an integral part of the team in global environment.
- Support project managers with effort estimations and resource planning.
- Support team leader in coaching, training and development team members

Requirement
- Education Required University and above
- Major Electrical and Electronics, Computer science
- Experience At least 5 years of experience in Physical Design
- Job related & requirements
• Experience in low power/multi voltage design and understanding of UPF.
• Worked on multiple tape-outs at ultra-deep sub-micron technologies, 28nm and smaller nodes, in complex multi-million gate designs.
• Deep knowledge of Synopsys or Cadence implementation tools and flow.
• Have hands on experience in completing RTL to GDSII flow, which includes synthesis, DFT, IO planning, floor-planning, power analysis, P&R, CTS, extraction, timing closure, physical verification, rail analysis etc.,
• Strong technical knowledge in microelectronics and/or system architectures.
• Knowledge on package design, ESD, integration of analog and mixed signal macros.
• Excellent debugging skills for design issues.
• Experience in using Perl and TCL/TK to achieve highly automated, reproducible and fast results.
- Other requirements good communication and interpersonal skills.
• Good at English
• Logical thinking
• Research and apply new technology
• Analytic and troubleshoot problem/
• Careful
• Ability to multi-task and can work under deadline pressure.