JD FOR DESIGN VERIFICATION:
- Plan the verification of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
- Create a constrained-random verification environment using SystemVerilog and UVM.
- Identify and write all types of coverage measures for stimulus and corner-cases.
- Debug tests with design engineers to deliver functionally correct design blocks.
- Close coverage measures to identify verification holes and to show progress towards tape-out.
Qualifications (Minimum qualifications):
- BS degree or equivalent practical experience.
- Experience in the verification of designs such as CPUs, networking or peripheral controllers.
- Experience with verification methodology such as UVM/OVM/VMM.
- Experience with SystemVerilog, SVA, C, C++ and functional coverage.
JD FOR DESIGN SERVICE:
- Front End
- Create vector related analysis, test synthesis / DFT / STA / sdc clean up / UPF clock
- Back End
- APR (Auto Place Route) / PV (Physical Verification), STA, UPF
- Experience of 3-10 years or more
- Priority candidates who have experience working in the Design Center
- Other conditions
- Know Korean or English
- Priority to candidates who have worked in a foreign enterprise
- Know Shell / Perl / Tcl / Python is advantage
- Priority to candidates with experience SoC Design Service